This invention relates to systems and methods for creating high voltage Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). More specifically, this invention relates to systems and methods of creating high voltage MOSFETs with graded extensions that provide a high breakdown voltage.
High voltages applied to the terminals of a MOSFET can cause breakdown in the transistor as a result of the high electric fields generated. FIG. 1A illustrates a cross section of a first prior art high voltage lateral DMOS transistor 100. Transistor 100 includes source 123, body 116, drain 113, and n-epitaxial layer 117. A disadvantage of transistor 100 is that it typically has a high threshold voltage (e.g., 1.5-5 volts) that is not compatible with low voltage (LV) CMOS technology.
FIG. 1B illustrates a cross section of a second prior art high voltage lateral DMOS transistor 130. Transistor 130 includes source 123, body 136, drain 113, and diffused n-type drain extension region 137. FIG. 1C illustrates a cross section of a third prior art high voltage lateral DMOS transistor 160. Transistor 160 includes source 123, body 116, drain 113, n-epitaxial layer 167, and N+ buried layer 169.
Transistors 100, 130 and 160 each include thick field oxide 111 and thin oxide 114. Thick field oxide 111 reduces the electric field on the drain side of gate 115. Thick field oxide 111 in transistors 100, 130, and 160 includes bird's beak encroachment 121. A disadvantage of transistors 100, 130, and 160 is that bird's beak 121 increases the ON-resistance RDS(ON) of transistor 100.
Transistors 100, 130, and 160 have a large overlap of the gate polysilicon over the drain extension region that results in an increase in the gate-to-drain capacitance. This overlap is a further disadvantage of the prior art, because it reduces the frequency response of the transistor.
For lateral DMOS 160 to have a drain source breakdown voltage BVdss greater than 100 volts, N-epitaxial layer 167 must be greater than 10 microns, which is not compatible with low voltage (LV) CMOS or LV BiCMOS processes. DMOS 160 also has a high output capacitance, because all of N-epitaxial layer 167 is coupled to the output of the transistor, which negatively affects the propagation delay and switching characteristics of the device.
Lateral DMOS transistors 100, 130, and 160 limit potential high breakdown voltages, because they use drain extensions with non optimized doping gradients. When doping is substantially constant throughout a transistor's drain between the gate and the N+ drain contact, the charge concentration of majority carriers is not optimized. Electric fields present in the drain region next to the gate are the same as the electric fields present in drain region next to the N+ drain contact region, increasing the possibility of breakdown at very high electric fields.